- EP102
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- 發布者：凌曄科技
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查看此店鋪所有供求信息 聯系人：陳小姐 電話：13544017528 手機：13544017528 地址：廣東省深圳市福田區中航路華強廣場C座13L 服務：  價格： 綜合： 營業時間：全年營業 QQ/微信/Skype： |
詳細信息
品牌：微驅
封裝：TSSOP56
批號：15+
數量：200
描述：Overview
EP102 is a high speed 6/8-bit LVDS receiver capable of receiving LVDS inputs at 112 Mhz clock rate. The chip supports single link transmission between the host and the flat panel display up to SXGA resolution. The chip converts the LVDS differential inputs into 18/24-bits RGB data outputs and 3 control outputs (Vsync, Hsync & DE). In 18-bit RGB applications, the 6-bit data can be output left or right justified from the 8-bit data output pins.
Feature
•Wide operating frequency range: 25 ~112 Mhz pixel rate
•Wide channel skew tolerance: 1/3 bit time
•Selectable left or right justified in 6-bit data output.
•No external components required
•Power Down Mode
•Single Power Supply (3.3V)
•Low profile 56 Lead TSSOP Package (Pb-free)
深圳市凌曄科技有限公司
廣東省深圳市福田區華強廣場C座13L
TEL：0755-83660559
QQ：869030400
E-mail：869030400@qq.com
封裝：TSSOP56
批號：15+
數量：200
描述：Overview
EP102 is a high speed 6/8-bit LVDS receiver capable of receiving LVDS inputs at 112 Mhz clock rate. The chip supports single link transmission between the host and the flat panel display up to SXGA resolution. The chip converts the LVDS differential inputs into 18/24-bits RGB data outputs and 3 control outputs (Vsync, Hsync & DE). In 18-bit RGB applications, the 6-bit data can be output left or right justified from the 8-bit data output pins.
Feature
•Wide operating frequency range: 25 ~112 Mhz pixel rate
•Wide channel skew tolerance: 1/3 bit time
•Selectable left or right justified in 6-bit data output.
•No external components required
•Power Down Mode
•Single Power Supply (3.3V)
•Low profile 56 Lead TSSOP Package (Pb-free)
深圳市凌曄科技有限公司
廣東省深圳市福田區華強廣場C座13L
TEL：0755-83660559
QQ：869030400
E-mail：869030400@qq.com
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